DRAMs having folded bit lines are well known, and typically are formed of rows or word lines and columns or bit lines, the columns each being formed of a complementary pair of the bit lines. Storage capacitors are located at the intersection of each word line and column, which store charge designative of zeros and ones. For example, the presence of a charge on a capacitor can signify the existence of a one and the absence of a charge can signify the presence of a zero. The capacitors are connected to the bit lines through access transistors which are enabled from the word lines.
In order to speed reading and writing of the memory, the bit lines are precharged to a voltage V.sub.BLP which is half of the supply voltage and the reference plate of the storage capacitor is charged to a voltage V.sub.cp which is half of the supply voltage. Precharging the bit lines to half the supply voltage reduces signal swing on the bit lines which reduces peak current and allows faster reading. Using V.sub.cp as the storage capacitor reference plate voltage reduces voltage stress on thin capacitor dielectrics.
In prior art DRAMs, separate circuits are required to generate the storage capacitor reference voltage V.sub.CP and the bit line precharge voltage V.sub.ELP. A low impedance drive is required for V.sub.BLP to maintain the bit line precharge level, while a high impedance drive is required for V.sub.cp to prevent voltage supply noise from charging the storage capacitor reference level and inadvertently enabling the access transistor. Using two separate circuits to generate V.sub.cp and V.sub.BLP results in V.sub.BLP not tracking the V.sub.cp voltage.